According to one technique for enhancing efficiency of a data processing system, instructions are executed simultaneously by multiple process devices connected through a bus to a common memory device. One or more of the process devices can have a resident cache memory for storing frequently accessed information without having to reaccess the common memory device each time such information is needed. Coherency techniques are used to maintain the integrity of information shared between the multiple process devices, particularly the integrity of information modified by one of the process devices. Also, one or more of the process devices can support pipelining and split-transaction operations through the bus.
Some previous techniques have attempted to transfer information between multiple buses. Nevertheless, typical previous techniques have failed to reliably achieve such information transfers without being subject to unresolvable deadlock conditions, particularly where the buses operate asynchronously relative to one another, or where one or more of the buses supports coherency techniques, pipelining, or split-transaction operations.
Thus, a need has arisen for a method and system for transferring information between multiple buses, in which information is reliably transferred between multiple buses operating asynchronously relative to one another. Also, a need has arisen for a method and system for transferring information between multiple buses, in which information transfers are not subject to unresolvable deadlock conditions. Further, a need has arisen for a method and system for transferring information between multiple buses, in which one or more of the buses supports coherency techniques, pipelining, or split-transaction operations.